1. Field of the Invention
The present invention relates to a semiconductor memory device and a control method thereof, and, more particularly relates to a semiconductor memory device having a redundant memory cell that replaces a defective normal memory cell, and a control method thereof.
2. Description of Related Art
DRAM (Dynamic Random Access Memory) is one of the most widely used semiconductor memory devices. In recent years, most of the used DRAMs are predominated by a synchronous DRAM in which a command is inputted in synchronism with a clock signal and data is inputted and outputted. Issuance of a command to the synchronous DRAM is performed as described below.
First, when performing a read operation, a row address is inputted in synchronism with an active command (ACT), and subsequently a column address is inputted in synchronism with a read command (READ). Thereby, read data is outputted from a data input/output pin. Meanwhile, when performing a write operation, the row address is inputted in synchronism with the active command (ACT), and subsequently a column address is inputted in synchronism with a write command (WRIT). Thereby, write data inputted to the data input/output pin is written. At the last stage of the read operation and the write operation, a precharge command (PRE) is inputted, and thereby a word line is reset.
The active command (ACT) selects the word line of a memory cell, which is an access target. The row address inputted in synchronism with the active command (ACT) is predecoded by a predecoder, and a predecode signal generated thereby is supplied to a driver circuit that drives the word line. In Japanese Patent Application Laid-open No. H9-320262, there is disclosed an example in which a holding circuit that holds a predecode signal is arranged for each memory cell.
Generally, the predecode signal is reset in response to issuance of the precharge command (PRE). It is for transitioning the predecode signal at a higher speed when the row address is inputted in synchronism with a subsequent active command (ACT). That is, when the predecode signal maintains its logical level corresponding to the active command (ACT) of last time, a rate of change of predecode signal is decreased due to the influence of coupling between signal wirings. On the other hand, when the predecode signal is once reset, the influence of the coupling is eliminated and the rate of change of predecode signal is accelerated.
However, when the predecode signal is reset, charges on the signal wirings are all flown out. Thus, when the predecode signal is reset at each time the precharge command (PRE) is issued, there is a problem of power consumption increase. Accordingly, a method for preventing an increase in power consumption resulting from resetting of a predecode signal while suppressing the decrease in access rate as small as possible has been desired.